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A computer has a single core processor having 8 General purpose registers and 8 additional special purpose registers.

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A computer has a single core processor having 8 General purpose registers and 8 additional special purpose registers. The machine has 64 KB RAM. The size of each register and memory word is 16 bits each. An instruction of the machine is of fixed length and is equal to two memory words. Each instruction of the machine has two operands – one memory operand and second register operand. Memory operand uses direct addressing; however, register operand can use either register direct or register indirect addressing. (Please note that if register operand uses indirect addressing, then stated register contains the address of the operand in the memory.) An instruction of a machine consists of operation code bits, One addressing mode bit and one register operand and one memory operand. The addressing mode bit specifies addressing mode as:

 Addressing mode bit |Register Operand | Memory Operand 
     0                                    Indirect                     Direct
     1                                    Direct                        Direct

Five of the special purpose registers perform the task as Program Counter (PC), Accumulator (AC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The size of Integer operands on the machine may be assumed to be of equal to size of accumulator register. In order to execute instructions the machine has an Instruction Register (IR) of size 32 bits as each instruction is of this size. Perform the following tasks for the machine.

(i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also indicate how many different operations can be coded for this machine. Give reasons in support of your answer. (3 Marks)

(ii) Put some valid values in certain registers and memory locations and demonstrate examples of different addressing modes of this machine. (1 Mark)

(iii)Assuming that the instructions are first fetched to Instruction Register (IR) and memory operands is brought to DR register; indirect operand is brought to AC; and result of operation is stored in the AC register; write and explain the sequence of micro-operations that are required for fetch cycle and execute cycle of an instruction which performs addition of two operands having addressing mode bits as 0. Please note that one of the operand is Indirect Register Operand and the second is a direct memory operand. Make and state suitable assumptions, if any.

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