# Q1. Design a two bit counter circuit that count from the state 00 to 10 only. The state 11 is ignored. The states of the counter, thus, may be 00, 01, 10, 00, 01, 10… Use J-K flip flop to design the circuit. You must design them using state transition diagram and Karnaugh's map.

, ,

To design a two-bit counter circuit that counts from 00 to 10 and ignores the state 11 using J-K flip-flops, you can follow these steps:

State Transition Diagram:

```

+-------+   J0   +-------+

|       |-------->|       |

|   00  |   K0   |   01  |

|       |<--------|       |

+-------+         +-------+

^ |   J1   +-------+

| +---------|       |

+-----------|   10  |

|   K1      |       |

+-----------+-------+

```

Karnaugh Maps for J and K Inputs:

For J0 and K0:

```

K0J0

----

00 |  0  0

01 |  1  0

10 |  0  1

11 |  -  -

```

For J1 and K1:

```

K1J1

----

00 |  1  0

01 |  0  0

10 |  0  1

11 |  -  -

```

Boolean Expressions:

```

J0 = Q0'

K0 = Q0

J1 = Q0Q1'

K1 = Q0'Q1

```

Circuit Implementation:

You can implement this circuit using J-K flip-flops. Let's denote the flip-flop outputs as Q0 and Q1.

```plaintext

+---+    +---+

--|J0K0|----|J1K1|---

+---+    +---+

|        |

|  +-----|-----+

|  |     |

|  |  +--|-----+   +-----+

|  |  |  |     |---|     |

|  |  +--|-----+   | 10  |

|  |     |         |     |

|  +-----|---------|     |

|        |         +-----+

+--------|-----------+

|

Q0Q1

```

This circuit uses two J-K flip-flops (J0K0 and J1K1) to implement the state transition diagram. The clock input is assumed to be a common clock signal shared by both flip-flops. The state changes according to the defined J and K inputs based on the current state.